1. Field of Invention
This invention is generally related to the field of data processing. In particular, it relates to address formation in an information processing system including logical address spaces and directory tables (e.g. a Translation Lookaside Buffer or TLB).
2. Description of Prior Art
The present invention involves the control of Translation Lookaside Buffers (TLBs) by user mode software. It also relates to the use of virtual memory to address a very large data object in a multi-processor computer system.
A good description of a computer system with virtual memory and Translation Lookaside Buffers can be found in U.S. Pat. No. 3,902,163 issued on Aug. 26, 1975 to Gene M. Amdahl, et al. Additional patents showing TLBs are U.S. Pat. Nos. 4,410,941, 5,109,335 and 5,155,834. The latter is notable because it shows a scheme for use in a multi-processor to keep TLB's coherent.
The problem of cache and TLB coherency goes back over 25 years as reflected in U.S. Pat. No. 3,771,137 issued to Robert Paul Barner on Nov. 6, 1973. Other more recent U.S. patents showing different schemes for TLB coherency are U.S. Pat. Nos. 4,442,487, 4,733,348, and 5,333,296. All prior art TLB coherency schemes can be characterized as aggressive. They all try to invalidate stale data ("TLB invalidates") as quickly and efficiently as possible. It would be fair to say that the general trend over the last 25 years has been to make the TLB invalidates happen more quickly with less overhead. The present invention, on the other hand, is not aggressive (is "lazy") about TLB invalidates and allows stale data to sit in the TLBs until user mode software determines that a TLB invalidate is required for correct operation of the application software. In fact, the last 25 years of prior art teach away from the present invention. They work hard to make sure that there is no stale data in the TLB while the present invention allows stale data to stay in the TLB as long as it will do no harm.
Again, the use of software to control cache consistency has been around for decades. U.S. Pat. No. 4,713,755 issued to William S. Worley of Dec. 15, 1987 is one example. U.S. Pat. No. 4,774,653 issued to David V. James on Sep. 27, 1988 shows a hybrid hardware/software method for maintaining a TLB. U.S. Pat. Nos. 5,493,660 and 5,539,892 show different schemes for software assisted TLB maintenance. All of the prior art software assisted TLB maintenance was done by operating system (or Kernel mode) software. In the present invention user-mode code is responsible for determining what TLB entries need to be invalidated, and when, and invokes kernel mode code to perform any invalidations only when required.
Again, addressing large data objects is old. U.S. Pat. No. 4,047,243 issued to Edsger W. Dijkstra on Sep. 6, 1977 shows one such scheme. U.S. Pat. No. 4,388,685 issued to Alan Kotok, et al on Jun. 14, 1983 shows a different scheme for extended virtual addressing. U.S. Pat. No. 4,731,734 issued to Ronald H. Gruner, et al on Mar. 15, 1988 shows, among other things, an object based addressing scheme for dealing with large data objects. More recently, U.S. Pat. No. 5,381,537 issued to Richard L. Baum on Jan. 10, 1995 shows a method for translating a large virtual address into a smaller conventional address as part of a TLB update. Again, all of the TLB updating is done either by hardware or Kernel mode operating system software.
Nothing in the prior art suggests doing any of the TLB maintenance in user mode where user mode software is responsible for the correctness of the TLB and certainly nothing suggests the unique combination of extended addressing, multi-processor support and lazy TLB invalidation of the present invention.